Cadence Design Systems and STMicroelectronics began a collaboration on the tape-out of a 7nm SerDes 56G VSR (very short-reach) for a System on Chip (SoC ) intended for the networking, cloud and data centre markets. For the SerDes 56G-VSR, Cadence provided the critical IP architecture, IP sub-blocks and related design support, leveraging its investment in 56G and 112G SerDes PAM4 technology; ST developed the complete SerDes core using its expertise in this area.
Cadence's broad IP portfolio, including SerDes PAM4 Multi-Rate at 112G, and state-of-the-art digital and signoff technology, as well as the Innovus implementation system, support Cadence's Intelligent System Design strategy, enabling customers to achieve excellence in SoC development.
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"Cadence's strong SerDes 112G fully meets the requirements for ASICs for networking and communications," said Flavio Benetti, general manager of the ASIC division at STMicroelectronics. "By combining Cadence's silicon-proven IP constituents with our deep knowledge of analog and SerDes mixed-signal design techniques, we were able to beat our customers' tough power targets. We value our continued collaboration and have selected Cadence as our preferred supplier for long-range SerDes IP 112G."
"Our successful collaboration with STMicroelectronics exemplifies how Cadence delivers SoC design excellence through our intelligent systems design strategy," said Babu Mandava, senior vice president and general manager of Cadence's IP group. "Our silicon-proven PAM4 SerDes IP portfolio, optimised for power, performance and area efficiency, used in conjunction with the Cadence Innovus implementation system, has enabled ST to achieve performance excellence and time-to-market advantage for their innovative designs."
