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What fuels the computational tsunami driven by AI, machine learning and big data

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Unlock new levels of computing performance with vertical power delivery    

By Ajith Jain, Vice President HPC Business Unit

As power levels of high-performance AI processors continue to increase and core voltages to decrease due to advanced process nodes, power system designers are challenged to manage impedance rise and voltage drops in power delivery networks (PDNs), voltage gradients across high-current and low-voltage processor power pins, transient performance specifications, and power losses.

In the case of cluster computing, where arrays of processors, which are very close to each other, are used to increase the speed and performance of machine learning, PDN complexity increases significantly because power delivery must be performed vertically from beneath the array.

Designing a PDN using the Vicor Factorized Power Architecture (FPA™) with current multipliers on the point-of-load instead of traditional voltage conversion techniques provides significant performance gains. This is made possible by the characteristics of point-of-load (PoL) power components: high current density, small number of components and, very importantly, flexibility in placement. PoL power components thus allow current to be delivered laterally and/or vertically to AI processor cores and memory circuits, significantly reducing PDN impedances.

Understanding peak current requirements with current power delivery networks

Modern GPUs have tens of billions of transistors, a number that grows with each new generation and product family, and that is made possible by smaller and smaller process node geometries. Improvements in processor performance then follow with each new generation, but all of this comes at a price, namely, the demand for power delivery, which, goes up, exponentially.

Figure 1 shows the dramatic increase in current requirements due to the reduced transistor geometry and core voltages.

Figure 1 - In most cases, power delivery is now the limiting factor in computing performance as new processors consume ever-increasing currents. Power delivery involves not only power distribution, but also efficiency, size, cost, and thermal performance.

Peak current demands of up to 2000A are now a typical requirement. In response to this power delivery challenge, some xPU companies are considering multi-rail options in which the main core power rails are divided into five or more lower current inputs. The PDN for each of these rails must still deliver high current while needing precise individual tuning, which puts some pressure on the density of the PDN and its physical location on the throttle board.

To further increase this complexity, the highly dynamic nature of machine learning workloads results in very high di/dt transients that last several microseconds. This creates stress across the PDN of a high-performance processor module or accelerator card.

The architecture of a typical power delivery network is highlighted in Figure 2.

Figure 2 - Typical PDN for high-performance processor.

Best practices for optimizing a power delivery network

The work of the Open Compute Project® (OCP®) consortium has helped establish a standard framework for the development design of rack-based and card-based processors. The Open Rack Standard V2.2 defines a 48V backplane server and operating voltage for open accelerator modules (OAMs) used primarily for artificial intelligence (AI) and machine learning workloads. To maintain compatibility with legacy 12V systems, the standard provides the capability to meet 12-to-48V and 48-to-12V requirements.

Focusing on the processor power supply, or PoL, is fraught with technical challenges. The technical advances highlighted in the previous section focused on the downward trend in voltage scaling, the tight requirements in core voltage tolerance, and the upward trend in current consumption. At the board level, the impact of these factors manifests itself in multiple ways.

The peak current densities encountered are extreme for any PCB. Power routing paths capable of these huge loads requires care. Highly dynamic workloads can create transient spiking voltages, which sophisticated processors find damaging and potentially destructive. However, a processor board has hundreds of other passive components, memory, and other ICs essential to its operation that also need 'positioning.

Then there are the I2R losses. Track lengths for the power path must be short. To achieve this, power conversion modules must be close to the processor to reduce track heating. The likelihood of PCB flexing due to processor load currents and localized thermal gradients requires stiffeners on the processor board. In addition, the power efficiency specifications of the converter should be as high as possible to avoid further thermal management problems.

Unleashes the power of the processor

Providing sufficient processor power today requires innovation to try to overcome the status quo. New ideas, architectures, topologies and technologies are the way to a more reliable and scalable power distribution network. Vicor's Factorized Power Architecture (FPA™) is the basis for providing more efficient power for today's unprecedented high performance computing needs.

Figure 3 - Factorized Power Architecture (FPA™) factors power into dedicated regulating and transforming functions. Both of these functions can be individually optimized and implemented to provide a high-density, high-efficiency solution.

Vicor's FPA divides the task of a power converter into the dedicated functions of regulation and transformation. A high efficiency and high density solution is achieved by separating and optimizing them individually. FPA in combination with the Sine Amplitude Converter (SAC™) topology is the basis for several innovative architectures that can help unleash the full power of today's high-performance processors.

Figure 4 - Leveraging FPA, Vicor minimizes "last inch" resistances with several patented solutions involving lateral power delivery (LPD) and vertical power delivery (VPD). All enable processors to achieve previously unattainable levels of performance to support today's exponentially growing HPC processing demands.

Vicor power converter technology leverages the unique Factorized Power Architecture that not only optimizes power converter efficiency, but also enables very low PDN losses associated with high-current, low-voltage power delivery to the PoL (ASIC or a CPU or GPU, etc.).

Lateral power delivery is an innovative technique in which the two current multipliers (Vicor VTM™ modules) flank the north and south side or the east and west side of the processor. This technique is preferred for load currents of ~800A at 0.8V nominal with associated 70µΩ PDN at 100°C. Using these numbers, we can calculate ~45W of power loss. A heat sink covering both the 2.8 mm high current multipliers and the processor as shown in the figure would be a good thermal solution. This architecture is excellent for powering accelerator graphics cards (OAM or otherwise), ASICs, and network APUs used in hyperscale data centers or supercomputer cabinets.

The Lateral-vertical power delivery technique is similar to lateral power delivery, but with one difference: only 70% of the power is delivered laterally using current multipliers side-by-side on the sides of the processor. An additional current multiplier on the underside of the processor will deliver the remaining 30% of the load current directly to the processor BGA. The side-by-side/vertical hybrid achieves a reduction in PDN loss by almost a factor of four! This technique also frees up space on the board to accommodate a second high-current rail (aux) or HBM memory rail on the top side of the board around the processor.

Vertical-lateral power delivery, on the other hand, takes advantage of pushing 50% of the load current through additional current multipliers on the underside of the processor. This technique provides an additional 50% reduction in PDN loss compared to the vertical-lateral approach. A 1200A design can now realize a PDN resistance of only 10µΩ, resulting in a power loss of less than 14.4W. In this case, the heatsink can be placed on both the top and bottom surfaces of the load if space permits. This architecture is particularly effective for applications that cannot accept components on the top side of the board to facilitate the interconnection of fast signals from the periphery of the ASIC. Examples include CPOs, NPOs, and network/broadband communication devices.

Vertical power delivery is the ideal solution in terms of delivering very high currents at low processor core voltages with the lowest PDN resistance. In this case, current multipliers and bypass capacitors are stacked on top of each other to form an integrated power module (geared current multiplier) that can be mounted directly under the processor by moving the bypass capacitor bank. Vicor GCMs are custom-built devices that map the current multiplier pinout to the AI BGA processor, as well as being able to provide all the necessary bypass capacitors within the module itself. This technique opens the top plane of the PCB for routing high-speed signals from the processor periphery to achieve a solution with maximum signal integrity. Applications such as CPO (Package hosting optical and network processors) and ASICs for high-speed signals can benefit from this power delivery technique.

Vicor architectures are flexible enough to be adapted to a wide variety of high-performance computing solutions. Vicor solutions can reduce motherboard resistors by up to 50 times and processing power pin counts by more than 10. Leveraging a factorized power architecture (FPA™), Vicor minimizes "last inch" resistors with patented solutions that combine lateral power delivery (LPD) and vertical power delivery (VPD). Both enable processors to achieve previously unattainable levels of performance to support today's exponentially growing HPC processing demands.

FPA architectures are unmatched in current density and power loss reduction through PDN. Proper architectures, topologies, and small module sizes are unique in the power industry, and for next-generation processors to operate at full capacity, they need power solutions that can adapt, scale, and deliver high-density power. Robust and reliable power modules along with innovative topologies are essential in a dynamic system where power requirements change rapidly. Artificial intelligence, machine learning, and edge computing will never have enough power for tomorrow using traditional power architectures. Meeting this ongoing need requires innovating today and being ready to adapt and scale for tomorrow using modular power.

For further information click here

Open Compute Project and OCP are registered trademarks of Open Compute Project.
FPA™ is a trademark of Vicor Corporation.

 

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