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Environment offering simultaneous optimization and full-chip signoff functions up to 10 times faster

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Cadence Design Systems has announced its new Cadence Certus solution, designed to address the increasing complexity and size challenges of chip-level design.

The Cadence Certus Closure Solution environment automates and accelerates the entire project timing closure cycle from weeks to hours, from signoff optimizations through routing to extraction and static timing analysis (STA).

The solution supports larger chip designs through unlimited capabilities, improving productivity levels up to 10 times over current methodologies and flows.

The Cadence Certus solution reduces the signoff bottlenecks and development complexity of today's emerging applications such as hyperscale computing, 5G communications, mobile, automotive and networking sectors.

Before the introduction of Cadence Certus, a chip closure flow involved long and tedious manual processes of chip assembly, timing analysis, and optimization with hundreds of views, which took designers months.

The new solution provides a fully automated and massively distributed environment that ensures superior levels of optimization and signoff.

This enablessimultaneous whole-chipoptimization with a shared engine between Cadence's Innovus Implementation System and Tempus Timing Signoff Solution, eliminating iteration cycles with sub-blocks, enabling designers to make rapid optimization and signoff decisions.

In addition, in conjunction with Cadence Cerebrus Intelligent Chip Explorer, designers can achieve further productivity improvements, starting from the individual block to the signoff of the chip in its entirety.

The Cadence Certus solution offers customers the following benefits:

  • Innovative scalable architecture: The distributed hierarchical signoff and optimization architecture of Cadence's Certus Closure solution is ideal for running in the cloud as well as in in-house data centers
  • Incremental signoff: Provides the functionality to flexibly restore and replace only the changed parts of the design, further speeding up the final signoff
  • Improved productivity: Fully automated flow reduces the need for lengthy and numerous iterations among multiple teams, providing faster time-to-market
  • SmartHub interface: Improved interactive GUI enables cross-probing for detailed debugging timing and to manage project closure at the "last mile" level
  • 3D-IC design efficiencies: Closely integrated with the Cadence Integrity 3D-IC solution, enabling users to close paths even between dies with heterogeneous processes

The Certus Closure solution supports Cadence's Intelligent System Design™ strategy, which enables the development of outstanding designs.

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